In recent years, nanoelectronics have been slowly shifting away from the traditional silicon-based von-Neumann architecture. In particular, not only non-planar integration concepts have become more and more common, but also a plethora of emerging post-CMOS nanomaterials, ranging from carbon nanotubes and graphene to memristors, have been introduced in the design process of modern nanoelectronics. At the same time, even the traditional CMOS-based semiconductor manufacturing process is moving towards 2nm transistors. In general, novel nanoelectronics are striving to allow for further miniaturization, increased performance, decreased energy consumption, and the implementation of more functionality.

Novel nanomaterials enable the implementation of advanced and more efficient computer components and peripherals, e.g., non-volatile computer memories (ReRAM and others), and advanced sensors, while at the same time allowing for their integration into conventional CMOS-based systems, in a symbiotic manner, creating hybrid devices that no longer fully adhere to the von-Neumann architecture. New computing paradigms are being developed facilitating these developments, in the form of neuromorphic and quantum computing, and collaborative, multi-layered systems of systems become the new norm, for example in the framework of the Internet of Things, cyber-physical systems, and the capabilities of machine learning and other artificial intelligence systems.

Within this context, new opportunities and challenges arise especially with regard to applications related to security and artificial intelligence. In the First Workshop on State-of-the-Art Nanoelectronics in the Framework of Security and Artificial Intelligence (NanoSecAI 2023), we aim to examine the hardware side of these developments, by exploring the interaction between novel and conventional state-of-the-art nanodevices, on the one side, and the concepts of security and artificial intelligence, on the other side.
In particular, we focus on the potential of state-of-the-art nanoelectronics to offer more secure and more intelligent applications and systems, on groundbreaking threats, risks, and attacks introduced by their utilisation, as well as advanced artificial intelligence systems either implemented using such nanoelectronics or employed to facilitate their design, integration, adoption, and/or use.

Call For Papers

The NanoSecAI workshop solicits paper submissions for oral and poster presentations in the following Areas:

• State-of-the-art conventional nanoelectronics with applications in the fields of AI and security
• Novel nanomaterials that allow for security and/or AI applications
• Secure devices, systems, and components using state-of-the-art nanoelectronics
• AI utilised to facilitate the design, integration, adoption, and/or use of nanodevices
• Attacks against state-of-the-art nanoelectronic implementations and/or systems incorporating them

Important Dates:

Paper Submission: May 02, 2023, 23:59 AOE  May 12, 2023, 23:59 AOE  May 19, 2023, 23:59 AOE
Acceptance Notification: June 01, 2023
Camera-ready Submission: June 17, 2023
Workshop Date: July 24, 2023

Paper Submission Instructions

Submitted contributions should be fully anonymous and follow the IEEE COINS guidelines to be potentially accepted.
Submissions may exceptionally be 4-8 pages long, following the IEEE double-column template (including the bibliography formatting), with the same page fees applying as in IEEE COINS.
Short papers of 4 pages are allowed 1 extra page, while longer papers of 6 pages are allowed an additional 2 pages.
Please submit your paper electronically in the PDF format using the following link on EasyChair (https://easychair.org/conferences/submission_new?a=29913856).
Accepted contributions that adhere to IEEE guidelines will be published in IEEE Xplore.

Our program is as follows. For more information, please send an e-mail using the following link.

15:45 - 16:30		Keynote by Prof. Dr. Ilia Polian: "Side-channel Vulnerabilities of Emerging Technologies: The Case of Memristors"
		Ilia Polian is a Full Professor and the Director of the Institute for Computer Architecture and Computer Engineering at the University of Stuttgart, Germany. He received his Diplom (MSc) and PhD degrees from the University of Freiburg, Germany, in 1999 and 2003, respectively. Prof. Polian co-authored over 200 scientific publications and received two Best Paper Awards. He is a Senior Member of IEEE. His scientific interests include hardware-oriented security, emerging architectures, test methods, and quantum computing. Keynote Abstract The transition of the underlying technology of electronic systems from today’s CMOS to emerging nano-devices is imminent. Such devices are promising improvements in area, performance and power consumption and offer unprecedented features, such as combining compute and storage operation within a single element. For practical applicability, security properties of architectures and circuits composed of nano-devices must be assessed and, if necessary, improved. While security was mainly an issue for cryptographic circuits in the past, today a large number of applications are storing and processing sensitive data that need to be protected as well. Examples are personal data, e.g., related to one’s health, or attributes for financial transactions. A well-understood set of physical attacks and applicable protections is known for CMOS circuits, and it is of interest how much of this knowledge is still valid for nano-architectures and where new approaches are necessary. In this talk, we focus on one emerging technology: memristive devices. A large number of such devices have been demonstrated experimentally, and they are useful for applications ranging from in-memory computing to neuromemetic hardware. Their beneficial features and capabilities, such as endurance and non-volatility of their state, can dialectically become disadvantages when it comes to potential security issues. We explore in-depth one main potential vulnerability: the side-channel analysis through the power channel. We show for different threat models how side-channel attacks that are effective in CMOS perform against memristive cryptographic constructions. We report both simulation and actual measured data of small fabricated circuits based on experimental devices. We propose a new approach called mPEM (memristive power estimation model) that is vastly effective for side-channel analysis of Memristive implementation. Using it, we demonstrate new side channels that did not exist in CMOS and also show that one protective solution does not work in the memristive domain for fundamental reasons. While our specific results apply to side-channel analysis of memristors, we believe that our generic approach will generalize to other classes of nano-devices as well and will make practical their security assessment once the underlying technology will mature sufficiently.
16:30 - 16:50		Oral Presentation: Segev Zaken, Keshet Meir, Leonid Azriel, Tomer Rindenau and Avi Mendelson, "Exploring the Limitations of the Property-based Hardware Trojan Detection Methods"
16:50 - 17:10		Oral Presentation: Sajjad Parvin, Sallar Ahmadi-Pour, Chandan Kumar Jha, Frank Sill Torres and Rolf Drechsler, "Lo-RISK: Design of a Low Optical Leakage and High Performance RISC-V Core"
17:10 - 17:45		Panel Discussion on State-of-the-Art Nanoelectronics in the Framework of Security and Artificial Intelligence: Prof. Dr. Elif Bilge Kavun, Prof. Dr. Ilia Polian, and Prof. Dr. Stavros G. Stavrinides
		Ilia Polian is a Full Professor and the Director of the Institute for Computer Architecture and Computer Engineering at the University of Stuttgart, Germany. He received his Diplom (MSc) and PhD degrees from the University of Freiburg, Germany, in 1999 and 2003, respectively. Prof. Polian co-authored over 200 scientific publications and received two Best Paper Awards. He is a Senior Member of IEEE. His scientific interests include hardware-oriented security, emerging architectures, test methods, and quantum computing. Elif Bilge Kavun holds the assistant professorship in Secure Intelligent Systems at the Faculty of Computer Science and Mathematics, University of Passau since October 2020. Previously, she was a Lecturer in Cybersecurity at The University of Sheffield (UK) and Digital Design Engineer for Crypto Cores at the Digital Security Solutions division, Infineon (Munich). She completed a PhD in Embedded Security in 2015 at the Faculty of Electrical Engineering and Information Technology, Ruhr University Bochum. Her research interests cover security of novel intelligent systems as well as traditional computing and embedded systems. She is also interested in secure hardware systems, design and implementation of cryptographic primitives, lightweight cryptography, and physical attacks & countermeasures. Stavros G. Stavrinides is a physicist with a MSc in Electronics and a PhD in Chaotic Electronics, all awarded by Aristotle University of Thessaloniki, Greece. He currently serves as a Professor of Nonlinear Dynamics and Electronics at Physics Department, International Hellenic University (IHU), Greece. His research interests include, non-exhaustively, chaotic electronics and their applications (with emphasis on hardware-security),analog and mixed-signal electronic circuits, experimental chaotic synchronization, nonlinear time series analysis, complex networks, Physical Unclonable Functions (PUF) and memristors. Prof. Stavrinides has authored or co-authored more than 100 journal and conference papers and 4 book chapters and edited 2 books. Finally, he has contributed, as a researcher, in several national (Greek) and international (EU, NATO) funded projects. He is an IEEE member, member of the Chua Memristor Center and Member of the Institute of Complexity of IHU.

Acknowledgement

This Workshop has been partially funded by the German Research Foundation – Deutsche ForschungsGemeinschaft (DFG), as part of the Projects "PUFMem: Intrinsic Physical Unclonable Functions from Emerging Non-Volatile Memories" (project number 440182124) and "NANOSEC: Tamper-Evident PUFs based on Nanostructures for Secure and Robust Hardware Security Primitives" (project number 439892735) of the Priority Program "Nano Security: From Nano-Electronics to Secure Systems" (SPP 2253).