In recent years, nanoelectronics have been slowly shifting away from the traditional silicon-based von-Neumann architecture. In particular, not only non-planar integration concepts have become more and more common, but also a plethora of emerging post-CMOS nanomaterials, ranging from carbon nanotubes and graphene to memristors, have been introduced in the design process of modern nanoelectronics. At the same time, even the traditional CMOS-based semiconductor manufacturing process is moving towards 2nm transistors. In general, novel nanoelectronics are striving to allow for further miniaturization, increased performance, decreased energy consumption, and the implementation of more functionality.

Novel nanomaterials enable the implementation of advanced and more efficient computer components and peripherals, e.g., non-volatile computer memories (ReRAM and others), and advanced sensors, while at the same time allowing for their integration into conventional CMOS-based systems, in a symbiotic manner, creating hybrid devices that no longer fully adhere to the von-Neumann architecture. New computing paradigms are being developed facilitating these developments, in the form of neuromorphic and quantum computing, and collaborative, multi-layered systems of systems become the new norm, for example in the framework of the Internet of Things, cyber-physical systems, and the capabilities of machine learning and other artificial intelligence systems.

Within this context, new opportunities and challenges arise especially with regard to applications related to security and artificial intelligence. In the First Workshop on State-of-the-Art Nanoelectronics in the Framework of Security and Artificial Intelligence (NanoSecAI 2023), we aim to examine the hardware side of these developments, by exploring the interaction between novel and conventional state-of-the-art nanodevices, on the one side, and the concepts of security and artificial intelligence, on the other side.
In particular, we focus on the potential of state-of-the-art nanoelectronics to offer more secure and more intelligent applications and systems, on groundbreaking threats, risks, and attacks introduced by their utilisation, as well as advanced artificial intelligence systems either implemented using such nanoelectronics or employed to facilitate their design, integration, adoption, and/or use.

Call For Papers

The NanoSecAI workshop solicits paper submissions for oral and poster presentations in the following Areas:

• State-of-the-art conventional nanoelectronics with applications in the fields of AI and security
• Novel nanomaterials that allow for security and/or AI applications
• Secure devices, systems, and components using state-of-the-art nanoelectronics
• AI utilised to facilitate the design, integration, adoption, and/or use of nanodevices
• Attacks against state-of-the-art nanoelectronic implementations and/or systems incorporating them

Important Dates:

Paper Submission: May 02, 2023, 23:59 AOE  May 12, 2023, 23:59 AOE  May 19, 2023, 23:59 AOE
Acceptance Notification: June 01, 2023
Camera-ready Submission: June 17, 2023
Workshop Date: July 23-25, 2023 (TBA)

Paper Submission Instructions

Submitted contributions should be fully anonymous and follow the IEEE COINS guidelines to be potentially accepted.
Submissions may exceptionally be 4-8 pages long, following the IEEE double-column template (including the bibliography formatting), with the same page fees applying as in IEEE COINS.
Short papers of 4 pages are allowed 1 extra page, while longer papers of 6 pages are allowed an additional 2 pages.
Please submit your paper electronically in the PDF format using the following link on EasyChair (https://easychair.org/conferences/submission_new?a=29913856).
Accepted contributions that adhere to IEEE guidelines will be published in IEEE Xplore.

Our program will be announced in the coming weeks.
If you would you like to be notified when the program is updated,
please send an e-mail using the following link.

Keynotes

TBA